This invention relates to data communications circuitry, and more particularly, to data communications circuitry with tolerance for jitter.
Integrated circuits often contain data communications circuitry. A transceiver on one integrated circuit may transmit data that is received by a transceiver at another integrated circuit.
The presence of jitter can adversely affect the performance of a communications link. Some links therefore use oversampling schemes to reduce the impact of jitter. In a typical oversampling scheme, oversampling circuitry is used at both the transmitting and receiving ends of the communications link. Following oversampling at a transmitter, the oversampled data is transmitted over the link. At the receiver, downsampling circuitry is used to reconstruct the original data stream. Although conventional oversampling schemes can help reduce the sensitivity of a communications link to the adverse impact of jitter, the need for oversampling circuitry at the transmitter can introduce unwanted complexity into a system.
It would therefore be desirable to be able to provide improved data communications circuitry such as communications circuitry that exhibits tolerance to jitter.